A 0.8μm CMOS 2.5Gbps Oversampling Receiver and Transmitter for Serial Links*

A receiver targeting OC-48 (2.488Gbps) serial data link has been designed and integrated in a 0.8μm CMOS process. An experimental receiving front end circuit demonstrates the viability of using multiple phased clocks to overcome the intrinsic gatespeed limitations in the demultiplexing (receiving) and multiplexing (transmitting) of serial data. To perform clock recovery, data is 3x oversampled so that transitions can be detected to determine bit boundaries. The design of a transmitter for the high-speed serial data is also described. The complete transceiver occupies a die area of ~3x3mm2. * This research was partially supported by Center for Integrated Systems, Stanford University and a gift from Sun Microsystems 1 A 0.8μm CMOS 2.5Gbps Oversampling Receiver and Transmitter for Serial Links Chih-Kong Ken Yang and Mark A. Horowitz Center for Integrated Systems Stanford University Stanford, CA 94305 Correspondence Address: Chih-Kong Ken Yang Center for Integrated Systems, #65 Stanford University Stanford, California 94305-4070 Phone: (415) 725-3730 FAX: (415) 725-6949